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imsh4gp12a1f2c imsh4gp23a1f2c imsh8gp22a1f2c 240-pin ddr3 registered modules with parity bit 4 gbyte and 8 gbyte rohs compliant advance internet data sheet rev. 0.50 january 2008
advance internet data sheet ddr3 registered dimm imsh[4g/8g]pxxa1f2c qag_techdoc_a4, 4.20, 2008-01-25 2 01292008-3x8m-8frf we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com imsh4gp12a1f2c, imsh4gp23a1f2c, imsh8gp22a1f2c revision history: 2008-01, rev. 0.50 page subjects (major chan ges since last revision) all new document.
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 3 01292008-3x8m-8frf 1overview this chapter gives an overview of the 240?pin registered ddr3 dual-in-line memory modules product family with parity bit for address and control bus and describes its main characteristics. 1.1 features ? 240-pin 8-byte ddr3 sdram registered dual-in-line memory modules with parity bit for address and control bus. ? module organization: two rank 512mb 72 and four rank 1024mb 72 chip organization: 2 256mb 4, 2 128mb 8. ? pc3-10600, pc3-8500 and pc3-6400 module speed grades. ? 8gb, 4gb modules built with 2gb (1gb dual-die) ddr3 sdrams in packages pg-tfbga-78 ? ddr3 sdrams with a single 1.5 v ( 0.075 v) power supply. ? asynchronous reset. ? programmable cas latency, cas write latency, additive latency, burst length and burst type. ? on-die-termination (odt) and dynamic odt for improved signal integrity. ? refresh, self refresh and power down modes. ? zq calibration for output driver and odt. ? system level timing calibration support via write leveling and multi purpose register (mpr) read pattern. ? serial presence detect with eeprom. ? on-dimm thermal sensor functionality. ? rdimm dimensions: 133.35 mm x 30 mm. ? based on standard reference raw cards: 'd', 'f' and 'g'. ? rohs compliant products 1) . table 1 performance tabl e for ddr3?1333 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. qimonda speed code ?13g ?13h unit note 1) 1) the available cl and cwl settings depend on t he sdram device speed bin. the cl setting and cwl setting result in maximum but also minimum clock frequency re quirements. when making a selecti on of operating clock frequency, bot h need to be fulfilled: requirem ents from cl setting as well as requirements from cwl setting. for details, refer to chapter 4.1 speed bins. module speed bin pc3 ?10600g ?10600h device speed bin ddr3 ?1333g ?1333h cl- n rcd - n rp 8-8-8 9-9-9 cl and cwl settings for maximum clock frequency cl = 8 cwl = 7 cl = 9 cwl = 7 mhz maximum clock frequency and data rate with above cl and cwl settings 667 1333 667 1333 mhz mb/s minimum clock frequency and data rate with above cl and cwl settings 533 1066 533 1066 mhz mb/s
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 4 01292008-3x8m-8frf table 2 performance table for ddr3?1066 and ddr3?800 1.2 description the qimonda imsh[4g/8g]pxxa1f2c are registered dimm (rdimm) family with 30 mm hei ght based on ddr3 sdram technology. dimms are available ecc modules in 512mb 72 (4gb), 1024mb 72 (8gb) organization and density, intended for mounting into 240 pin connector sockets. the memory array is designed with 2gb (1gb dual-die) double data rate (ddr3) synchronous drams. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. de-couplin g capacitors, stub resistors, calibration resistors and termination resistors are mounted on the pcb board. the dimms feat ure serial presence detect based on a 256 byte serial eeprom device using the 2-pin i 2 c protocol. the first 176 bytes are programmed with module specific spd data. qimonda speed code ?10f ?10g ?08d ?08e unit note 1) 1) the available cl and cwl settings depend on t he sdram device speed bin. the cl setting and cwl setting result in maximum but also minimum clock frequency re quirements. when making a selecti on of operating clock frequency, bot h need to be fulfilled: requirem ents from cl setting as well as requirements from cwl setting. for details, refer to chapter 4.1 speed bins. module speed bin pc3 ?8500f ?8500g ?6400d ?6400e device speed bin ddr3 ?1066f ?1066g ?800d ?800e cl- n rcd - n rp 7-7-7 8-8-8 5-5-5 6-6-6 cl and cwl settings for maximum clock frequency cl = 7 cwl = 6 cl = 8 cwl = 6 cl = 5 cwl = 5 cl = 6 cwl = 5 mhz maximum clock frequency and data rate with above cl and cwl settings 533 1066 533 1066 400 800 400 800 mhz mb/s minimum clock frequency and data rate with above cl and cwl settings 400 800 400 800 300 600 300 600 mhz mb/s
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 5 01292008-3x8m-8frf table 3 product information for modules without heat spreader qimonda part number compliance code description 4096 mbyte registered dimm imsh4gp12a1f2c imsh4gp12a1f2c-08d 4gb 2r 4 pc3?6400p?5?xx?d0 240-pin 4096 mbyte ddr3 registered dimm with two rank and on-dimm thermal sensor. the memory rank consists of eighteen ddr3 components in x4 organization. standard reference card d is used on this assembly used ddr3 sdram component part number: issh2g-12a1f2c density: 2gbit (1gbit dual die) organization: 2 256mbit 4 address bits (row/column/bank): 14/11/3 imsh4gp12a1f2c-08e 4gb 2r 4 pc3?6400p?6?xx?d0 imsh4gp12a1f2c-10f 4gb 2r 4 pc3?8500p?7?xx?d0 imsh4gp12a1f2c-10g 4gb 2r 4 pc3?8500p?8?xx?d0 imsh4gp12a1f2c-13g 4gb 2r 4 pc3?10600p?8?xx?d0 imsh4gp12a1f2c-13h 4gb 2r 4 pc3?10600p?9?xx?d0 4096 mbyte registered dimm imsh4gp23a1f2c imsh4gp23a1f2c-08d 4gb 4r 8 pc3?6400p?5?xx?g0 240-pin 4096 mbyte ddr3 registered dimm with four ranks and on-dimm thermal sensor. each memory rank consists of nine ddr3 components in x8 organization. standard reference card g is used on this assembly used ddr3 sdram component part number: issh2g-13a1f2c density: 2gbit (1gbit dual die) organization: 2 128mbit 8 address bits (row/column/bank): 14/10/3 imsh4gp23a1f2c-08e 4gb 4r 8 pc3?6400p?6?xx?g0 imsh4gp23a1f2c-10f 4gb 4r 8 pc3?8500p?7?xx?g0 imsh4gp23a1f2c-10g 4gb 4r 8 pc3?8500p?8?xx?g0 imsh4gp23a1f2c-13g 4gb 4r 8 pc3?10600p?8?xx?g0 imsh4gp23a1f2c-13h 4gb 4r 8 pc3?10600p?9?xx?g0 8192 mbyte registered dimm imsh8gp22a1f2c imsh8gp22a1f2c-08d 8gb 4r 4 pc3?6400p?5?xx?f0 240-pin 8192 mbyte ddr3 registered dimm with four rank and on-dimm thermal sensor. the memory rank consists of eighteen ddr3 components in x4 organization. standard reference card f is used on this assembly used ddr3 sdram component part number: issh2g-12a1f2c density: 2gbit (1gbit dual die) organization: 2 256mbit 4 address bits (row/column/bank): 14/11/3 IMSH8GP22A1F2C-08E 8gb 4r 4 pc3?6400p?6?xx?f0 imsh8gp22a1f2c-10f 8gb 4r 4 pc3?8500p?7?xx?f0 imsh8gp22a1f2c-10g 8gb 4r 4 pc3?8500p?8?xx?f0 imsh8gp22a1f2c-13g 8gb 4r 4 pc3?10600p?8?xx?f0 imsh8gp22a1f2c-13h 8gb 4r 4 pc3?10600p?9?xx?f0
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 6 01292008-3x8m-8frf table 4 product information for modules with heat spreader qimonda part number compliance code description 4096 mbyte registered dimm imhh4gp12a1f2c imhh4gp12a1f2c-08d 4gb 2r 4 pc3?6400p?5?xx?d0 240-pin 4096 mbyte ddr3 registered dimm with two rank and on-dimm thermal sensor. the memory rank consists of eighteen ddr3 components in x4 organization. standard reference card d is used on this assembly used ddr3 sdram component part number: issh2g-12a1f2c density: 2gbit (1gbit dual die) organization: 2 256mbit 4 address bits (row/column/bank): 14/11/3 imhh4gp12a1f2c-08e 4gb 2r 4 pc3?6400p?6?xx?d0 imhh4gp12a1f2c-10f 4gb 2r 4 pc3?8500p?7?xx?d0 imhh4gp12a1f2c-10g 4gb 2r 4 pc3?8500p?8?xx?d0 imhh4gp12a1f2c-13g 4gb 2r 4 pc3?10600p?8?xx?d0 imhh4gp12a1f2c-13h 4gb 2r 4 pc3?10600p?9?xx?d0 4096 mbyte registered dimm im h h4gp23a1f2c imhh4gp23a1f2c-08d 4gb 4r 8 pc3?6400p?5?xx?g0 240-pin 4096 mbyte ddr3 registered dimm with four ranks and on-dimm thermal sensor. each memory rank consists of nine ddr3 components in x8 organization. standard reference card g is used on this assembly used ddr3 sdram component part number: issh2g-13a1f2c density: 2gbit (1gbit dual die) organization: 2 128mbit 8 address bits (row/column/bank): 14/10/3 imhh4gp23a1f2c-08e 4gb 4r 8 pc3?6400p?6?xx?g0 imhh4gp23a1f2c-10f 4gb 4r 8 pc3?8500p?7?xx?g0 imhh4gp23a1f2c-10g 4gb 4r 8 pc3?8500p?8?xx?g0 imhh4gp23a1f2c-13g 4gb 4r 8 pc3?10600p?8?xx?g0 imhh4gp23a1f2c-13h 4gb 4r 8 pc3?10600p?9?xx?g0
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 7 01292008-3x8m-8frf 2 configuration 2.1 pin configuration table 5 pin configuration of ddr3 rdimm - 240 pins pin name eda signal name 1) pin no. pin type buffe r type function clock signals ck0 ck0_t 184 i sstl differnetial clock inputs [1:0] ck0 ck0_c 185 i sstl ck1 ck1_t 63 i sstl ck1 ck1_c 64 i sstl control signals cke0 cke0 50 i sstl clock enable [1:0] cke1/nc cke1 169 i sstl odt0 odt0 195 i sstl on-die termination [1:0] odt1/nc odt1 77 i s0 s0_n 193 i sstl chip select [3:0] s1 s1_n 76 i sstl s2 s2_n 79 i sstl s3 s3_n 198 i sstl command signals ras ras_n 192 i sstl row address strobe cas cas_n 74 i sstl column address strobe we we_n 73 i sstl write enable bank address signals ba0 ba0 71 i sstl bank address bus[2:0] ba1 ba1 190 i sstl ba2 ba2 52 i sstl address signals a0 a0 188 i sstl address bus [15:0] a1 a1 181 i sstl a2 a2 61 i sstl
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 8 01292008-3x8m-8frf a3 a3 180 i sstl address bus [15:0] a4 a4 59 i sstl a5 a5 58 i sstl a6 a6 178 i sstl a7 a7 56 i sstl a8 a8 177 i sstl a9 a9 175 i sstl a10/ap a10 70 i sstl a11 a11 55 i sstl a12/bc a12 174 i sstl a13 a13 196 i sstl a14 a14 172 i sstl a15 a15 171 i sstl data signals dq0 dq0 3 i/o sstl data bus [63:0] dq1 dq1 4 i/o sstl dq2 dq2 9 i/o sstl dq3 dq3 10 i/o sstl dq4 dq4 122 i/o sstl dq5 dq5 123 i/o sstl dq6 dq6 128 i/o sstl dq7 dq7 129 i/o sstl dq8 dq8 12 i/o sstl dq9 dq9 13 i/o sstl dq10 dq10 18 i/o sstl dq11 dq11 19 i/o sstl dq12 dq12 131 i/o sstl dq13 dq13 132 i/o sstl dq14 dq14 137 i/o sstl dq15 dq15 138 i/o sstl dq16 dq16 21 i/o sstl dq17 dq17 22 i/o sstl dq18 dq18 27 i/o sstl dq19 dq19 28 i/o sstl dq20 dq20 140 i/o sstl dq21 dq21 141 i/o sstl dq22 dq22 146 i/o sstl dq23 dq23 147 i/o sstl dq24 dq24 30 i/o sstl pin name eda signal name 1) pin no. pin type buffe r type function
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 9 01292008-3x8m-8frf dq25 dq25 31 i/o sstl data bus [63:0] dq26 dq26 36 i/o sstl dq27 dq27 37 i/o sstl dq28 dq28 149 i/o sstl dq29 dq29 150 i/o sstl dq30 dq30 155 i/o sstl dq31 dq31 156 i/o sstl dq32 dq32 81 i/o sstl dq33 dq33 82 i/o sstl dq34 dq34 87 i/o sstl dq35 dq35 88 i/o sstl dq36 dq36 200 i/o sstl dq37 dq37 201 i/o sstl dq38 dq38 206 i/o sstl dq39 dq39 207 i/o sstl dq40 dq40 90 i/o sstl dq41 dq41 91 i/o sstl dq42 dq42 96 i/o sstl dq43 dq43 97 i/o sstl dq44 dq44 209 i/o sstl dq45 dq45 210 i/o sstl dq46 dq46 215 i/o sstl dq47 dq47 216 i/o sstl dq48 dq48 99 i/o sstl dq49 dq49 100 i/o sstl dq50 dq50 105 i/o sstl dq51 dq51 106 i/o sstl dq52 dq52 218 i/o sstl dq53 dq53 219 i/o sstl dq54 dq54 224 i/o sstl dq55 dq55 225 i/o sstl dq56 dq56 108 i/o sstl dq57 dq57 109 i/o sstl dq58 dq58 114 i/o sstl dq59 dq59 115 i/o sstl dq60 dq60 227 i/o sstl dq61 dq61 228 i/o sstl dq62 dq62 233 i/o sstl dq63 dq63 234 i/o sstl pin name eda signal name 1) pin no. pin type buffe r type function
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 10 01292008-3x8m-8frf cb0 cb0 39 i/o sstl check bit [7:0] cb1 cb1 40 i/o sstl cb2 cb2 45 i/o sstl cb3 cb3 46 i/o sstl cb4 cb4 158 i/o sstl cb5 cb5 159 i/o sstl cb6 cb6 164 i/o sstl cb7 cb7 165 i/o sstl dqs0 dqs0_t 7 i/o sstl data strobe signals [17:0] dqs0 dqs0_c 6 i/o sstl dqs1 dqs1_t 16 i/o sstl dqs1 dqs1_c 15 i/o sstl dqs2 dqs2_t 25 i/o sstl dqs2 dqs2_c 24 i/o sstl dqs3 dqs3_t 34 i/o sstl dqs3 dqs3_c 33 i/o sstl dqs4 dqs4_t 85 i/o sstl dqs4 dqs4_c 84 i/o sstl dqs5 dqs5_t 94 i/o sstl dqs5 dqs5_c 93 i/o sstl dqs6 dqs6_t 103 i/o sstl dqs6 dqs6_c 102 i/o sstl dqs7 dqs7_t 112 i/o sstl dqs7 dqs7_c 111 i/o sstl dqs8 dqs8_t 43 i/o sstl dqs8 dqs8_c 42 i/o sstl (t)dqs9 dqs9_t 125 i/o sstl (t)dqs9 dqs9_c 126 i/o sstl (t)dqs10 dqs10_t 134 i/o sstl (t)dqs10 dqs10_c 135 i/o sstl (t)dqs11 dqs11_t 143 i/o sstl (t)dqs11 dqs11_c 144 i/o sstl (t)dqs12 dqs12_t 152 i/o sstl (t)dqs12 dqs12_c 153 i/o sstl (t)dqs13 dqs13_t 203 i/o sstl (t)dqs13 dqs13_c 204 i/o sstl (t)dqs14 dqs14_t 212 i/o sstl (t)dqs14 dqs14_c 213 i/o sstl (t)dqs15 dqs15_t 221 i/o sstl pin name eda signal name 1) pin no. pin type buffe r type function
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 11 01292008-3x8m-8frf (t)dqs15 dqs15_c 222 i/o sstl data strobe signals [17:0] (t)dqs16 dqs16_t 230 i/o sstl (t)dqs16 dqs16_c 231 i/o sstl (t)dqs17 dqs17_t 161 i/o sstl (t)dqs17 dqs17_c 162 i/o sstl eeprom and thermal sensor scl scl 118 i cmo s serial bus clock sda sda 238 i/o od serial data bus sa0 sa0 117 i cmo s serial address select bus [2:0] sa1 sa1 237 i cmo s sa2 sa2 119 i cmo s power supply v dd vdd 51, 54, 57, 60, 62, 65, 66, 69, 72, 75, 78, 170, 173, 176, 179, 182, 183, 186, 189, 191, 194, 197 pwr - power supply pin name eda signal name 1) pin no. pin type buffe r type function
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 12 01292008-3x8m-8frf v ss vss 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 80, 83, 86, 89,92, 95, 98, 101, 104, 107, 110, 113, 116, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 199, 202, 205, 208, 211, 214, 217, 220, 223, 226, 229, 232, 235, 239 gnd - ground v ref.dq vrefdq 1 ai - reference voltage v ref.ca vrefca 67 ai - reference voltage v tt vtt 48, 49, 120 , 240 pwr - termination voltage v ddspd vddspd 236 - eeprom and thermal sensor power supply other pins reset reset_n 168 i asynchronous reset err_out err_out_n 53 o od err_out par_in par_in 68 i par_in pin name eda signal name 1) pin no. pin type buffe r type function
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 13 01292008-3x8m-8frf table 6 abbreviations for pin type table 7 abbreviations for buffer type event event_n 187 o od event nc nc 79, 126, 135, 144, 153, 162, 167, 198, 204, 213, 222, 231, -- not connected 1) the eda (electronic design automation) signal name is used in qimonda simulati on models such as ebd (electronic board description). abbreviation description i standard input pin only. digital levels. o standard output pin only - digital levels. i/o i/o is a bidirectional input/output signal. ai input - analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tri-state, and allows multiple devices to share as a wire-or. pin name eda signal name 1) pin no. pin type buffe r type function
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 14 01292008-3x8m-8frf figure 1 pin configuration rdimm - 240 pin 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 5()'4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 &% '46 9 66 &% 9 77 &.( %$ 9 '' $ $ 9 '' 9 '' &. 9 '' 3dub,q $$3 9 '' &$6 6 9 '' 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 6&/ 9 77 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 &% 9 66 '46 &% 9 66 9 77 9 '' (uub2xw $ 9 '' $ $ &. 9 '' 9 5()&$ 9 '' %$ :( 9 '' 2'71& 61& '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 6$ 6$9 66 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 '4 7'46 9 66 '4 '4 9 66 7'46 '4 9 66 '4 9 66 7'46 '4 9 66 '4 7'46 9 66 '4 '4 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 7'46 '4 9 66 '4 7'46 9 66 '4 &% 9 66 7'46 &% 9 66 5(6(7 9 '' $ $%& 9 '' $ $ 9 '' &. 9 '' $ %$ 5$6 9 ''4 $ 61& '4 9 66 7'46 '4 9 66 '4 7'46 9 66 '4 '4 9 66 7'46 '4 9 66 '4 7'46 9 66 '4 9 ''63' 6'$ 9 77 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 7'46 9 66 '4 '4 9 66 7'46 '4 9 66 &% 7'46 9 66 &% 1& &.( $ 9 '' $ $ 9 '' $ 9 '' &. (9(17 9 '' 9 '' 6 2'7 9 '' 9 66 '4 7'46 9 66 '4 '4 9 66 7'46 '4 9 66 '4 7'46 9 66 '4 '4 9 66 7'46 '4 9 66 6$ 9 66 ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 033+ 7)ru['5$0rqo\ 3lqdqg3lqwhuplqdwhgzlwk?
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 15 01292008-3x8m-8frf 3 operating conditions 3.1 absolute maximum ratings table 8 absolute maximum ratings table 9 environmental parameters attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. parameter symbol rating unit note min. max. voltage on v dd pin relative to v ss v dd ?0.4 +1.975 v 1) 1) v dd and v ddq must be within 300mv of each other at all times. v refdq and v refca must not be greater than 0.6 x v ddq . when v dd and v ddq are less than 500 mv, v refdq and v refca may be equal or less than 300 mv. voltage on v ddq pin relative to v ss v ddq ?0.4 +1.975 v voltage on any pin relative to v ss v in , v out ?0.4 +1.975 v parameter symbol rating unit note min. max. operating temperature t opr ?? c 1) 1) device designer must meet the case temperat ure specification for i ndividual module components. operating humidity (relative) h opr 10 90 % storage temperature t stg ?50 +100 c 2) 2) storage temperature is the case surface temperature on the center/top side of the sdram mentioned in qimonda component datash eet. storage humidity (without condensation) h stg 595 % barometric pressure (operating and storage) p bar 69 105 kpascal 3) 3) up to 9850 ft.
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 16 01292008-3x8m-8frf table 10 dram component operating temperature range 3.2 recommended dc operating conditions table 11 dc operating conditions parameter symbol rating unit note min. max. normal operating temperature range t oper 085 c 1)2) 1) operating temperature t oper is the case surface temperature on the center / top side of the sdram mentioned.. 2) the normal temperature range specifies the temperat ures where all sdram spec ification will be supported. extended temperature range 85 95 c 1)3) 3) some application require operation of the dram in the extended temperature range between 85 q c and 95 q c operating temperature. for more details please refer to qimonda component datasheet. parameter symbol min. typ. max. unit note supply voltage v dd 1.425 1.5 1.575 v 1)2) 1) v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together 2) under all conditions v ddq must be less than or equal to v dd . supply voltage for eeprom and thermal sensor v dd.spd 3.03.33.6v 1)2) supply voltage for output v ddq 1.425 1.5 1.575 v 1)2) reference voltage for dq, dm inputs v refdq.dc 0.49 x v dd 0.5 x v dd 0.51 x v dd v 3)4) 3) the ac peak noise on v ref may not allow v ref to deviate from v ref.dc by more than 1% v dd (for reference: approx. 15 mv). 4) for reference: approx. v dd /2 15 mv. reference voltage for add, cmd inputs v refca.dc 0.49 x v dd 0.5 x v dd 0.51 x v dd v 3)4) terminal voltage v tt 0.49 x v dd 0.5 x v dd 0.51 x v dd v external calibration resistor connected from zq pin to ground r zq 237.6 240.0 242.4 : 5) 5) the external calibration resistor r zq can be time-shared among drams in multi-rank dimms.
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 17 01292008-3x8m-8frf 4 speed bins and timing parameters ac timings are provided with ck/ck and dqs/dqs differential slew rate of 2.0 v/ns. timings are further provided for calibrated ocd driv e strength. the ck/ck input reference level (for timing referenced to ck / ck ) is the point at which ck and ck cross.the dqs/dqs reference level (for timing referenced to dqs/dqs ) is the point at which dqs and dqs cross.inputs are not re cognized as valid until v ref stabilizes. during the period before v ref.ca and v refdq stabilizes, cke = 0.2 x v ddq is recognized as low. the output timing reference voltage level is v tt .for details of all relevant ac timing parameters see the qimonda ddr3 component datasheet. 4.1 speed bins the following tables show ddr3 speed bins and relevant timing parameters. other timi ng parameters are provided in the following chapter. the absolute specification for all speed bins is t oper and v dd = v ddq = 1.5 v +/-0.075 v. in addition the following general notes apply. general notes for speed bins: ? the cl setting and cwl setting result in t ck.avg.min and t ck.avg.max requirements. when making a selection of t ck.avg , both need to be fulfiled: requirements from cl setting as well as requirements from cwl setting. ? t ck.avg.min limits: since cas latency is not purely analog - data and strobe output are syn chronized by the dll - all possible intermediate frequencies may not be provided. an application should use the next smaller standard t ck.avg value (2.5, 1.875, 1.5, or 1. 25 ns) when calculating cl [nck] = t aa [ns] / t ck.avg [ns], rounding up to the next ?supported cl?. ? t ck.avg.max limits: calculate t ck.avg = t aa.max / clselected and round the resulting t ck.avg down to the next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns or 1.25 ns). this result is t ck.avg.max corresponding to clselected. ? ?reserved? settings are not a llowed. user must program a different value. ? any ddr3-1066 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization. ? any ddr3-1333 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization. ? any ddr3-1600 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization. table 12 ddr3?800 speed bins speed bin ddr3-800d ddr3-800e unit note cl- n rcd - n rp 5-5-5 6-6-6 qag partnumber extension -08d -08e parameter symbol min. max. min. max. internal read command to first data t aa 12.5 20.0 15.0 20.0 ns 1) act to internal read or write delay time t rcd 12.5 ? 15.0 ? ns 1) pre command period t rp 12.5 ? 15.0 ? ns 1) act to act or ref command period t rc 50.0 ? 52.5 ? ns 1) supported cl settings sup_cl 5, 6 6 n ck 1) supported cwl settings sup_cwl 5 5 n ck 1)
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 18 01292008-3x8m-8frf table 13 ddr3?1066 speed bins average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 ns 1)2) 1) please refer to "general notes for speed bins" at beginning of this chapter. 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. speed bin ddr3-1066e ddr3-1066f ddr3-1066g unit note cl- n rcd - n rp 6-6-6 7-7-7 8-8-8 qag partnumber extension -10e -10f -10g parameter symbol min. max. min. max. min. max. internal read command to first data t aa 11.25 20.0 13.125 20.0 15.0 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 11.25 ? 13.125 ? 15.0 ? ns 1) pre command period t rp 11.25 ? 13.125 ? 15.0 ? ns 1) act to act or ref command period t rc 48.75 ? 50.625 ? 52.5 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8 6, 7, 8 6, 8 n ck 1) supported cwl settings sup_cwl 5, 6 5, 6 5, 6 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 1.875 2.5 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 1.875 2.5 reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 ns 1)2) speed bin ddr3-800d ddr3-800e unit note cl- n rcd - n rp 5-5-5 6-6-6 qag partnumber extension -08d -08e parameter symbol min. max. min. max.
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 19 01292008-3x8m-8frf table 14 ddr3?1333 speed bins speed bin ddr3- 1333g ddr3- 1333h ddr3-1333j unit note cl- n rcd - n rp 8-8-8 9-9-9 10-10-10 qag partnumber extension -13g -13h -13j parameter symbol min. max. min. max. min. max. internal read command to first data t aa 12.0 20.0 13.5 20.0 15.0 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 12.0 ? 13.5 ? 15.0 ? ns 1) pre command period t rp 12.0 ? 13.5 ? 15.0 ? ns 1) act to act or ref command period t rc 48.0 ? 49.5 ? 51.0 ? ns 1) supported cl settings s up_cl 5, 6, 7, 8, 9, 10 6, 8, 9, 10 6, 8, 10 n ck 1) supported cwl settings sup_cwl 5, 6, 7 5, 6, 7 5, 6, 7 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 5; cwl = 7 t ck.avg.cl05.cwl07 reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 7 t ck.avg.cl06.cwl07 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 7 t ck.avg.cl07.cwl07 reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 ns 1)2) average clock period with cl = 8; cwl = 7 t ck.avg.cl08.cwl07 1.5 1.875 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 5 t ck.avg.cl09.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 6 t ck.avg.cl09.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 7 t ck.avg.cl09.cwl07 1.5 1.875 1.5 1.875 reserved ns 1)2) average clock period with cl = 10; cwl = 5 t ck.avg.cl10.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 10; cwl = 6 t ck.avg.cl10.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 10; cwl = 7 t ck.avg.cl10.cwl07 1.5 1.875 1.5 1.875 1.5 1.875 ns 1)2)
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 20 01292008-3x8m-8frf 5 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 15 ?imsh4gp12a1f2c? on page 20 ? table 16 ?imsh4gp23a1f2c? on page 20 ? table 17 ?imsh8gp22a1f2c? on page 21 ? table 18 ?imhh4gp12a1f2c? on page 21 ? table 19 ?imhh4gp23a1f2c? on page 21 table 15 imsh4gp12a1f2c table 16 imsh4gp23a1f2c 7%' 7%'
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 21 01292008-3x8m-8frf table 17 imsh8gp22a1f2c table 18 imhh4gp12a1f2c table 19 imhh4gp23a1f2c 7%' 7%' 7%'
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 22 01292008-3x8m-8frf 6 package outline diagrams figure 2 package outline lg-dim-240-094 r/c d note: sdram component outlines are symbolic representation of the device placement. for actual sdram outline details please refer to sdram component data sheet. figure 3 package outline lg-dim-240-095 r/c f note: sdram component outlines are symbolic representation of the device placement. for actual sdram outline details please refer to sdram component data sheet. 7%' 7%'
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 23 01292008-3x8m-8frf figure 4 package outline lg-dim-240-096 r/c g note: sdram component outlines are symbolic representation of the device placement. for actual sdram outline details please refer to sdram component data sheet. 7%'
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 24 01292008-3x8m-8frf 7 product type nomenclature for reference the applicable qimonda ddr3 dimm module nomenclature is listed in this chapter. table 20 example: ddr3 1gbyte registered module table 21 ddr3 dimm nomenclature field number 1+2 3 4 5+6 7 8 9 10+11 12+13 14 15 16+17 18 qimonda product type im s h 4g p 1 2 a1 f2 c ? 08 e field description value coding 1+2 qimonda identifier im qimonda memory modules 3 power or application s standard h heat spreader l low power 4 product family h ddr3 5+6 density 51 512 mbytes 1g 1024 mbytes 2g 2048 mbytes 4g 4096 mbytes 7 module type / ecc support u 240 pin unbuffered dimms - non-ecc e 240 pin unbuffered dimms - ecc s 204 pin small outline dimms - non-ecc r 240 pin registered dimms - ecc p 240 pin registered dimms with parity bit - ecc 8 number of ranks 0 one rank of sdrams 1 two ranks of sdrams 2 four ranks of sdrams 9 dram device number of ios 2 4 components (2 2 ) 3 8 components (2 3 ) 4 16 components (2 4 ) 10+11 die revision a1 first 12+13 package f1 planar fbga, lead- and halogen-free f2 dual die fbga, lead- and halogen-free 14 temperature range c commercial (0 c - 95 c) 15 thermal sensor t modules with thermal sensor
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 25 01292008-3x8m-8frf 16+17 band width 08 pc3?6400, 6.4 gb/s, t ck = 2.5 ns, f ck =400 mhz 10 pc3?8500, 8.5 gb/s, t ck = 1.875 ns, f ck =533 mhz 13 pc3?10600, 10,66 gb/s, t ck = 1.5 ns, f ck =667 mhz 16 pc3?12800, 12,8 gb/s, t ck = 1.25 ns, f ck =800 mhz 18 latencies d cl?rcd?rp = 5?5?5 e cl?rcd?rp = 6?6?6 f cl?rcd?rp = 7?7?7 g cl?rcd?rp = 8?8?8 h cl?rcd?rp = 9?9?9 j cl?rcd?rp = 10?10?10 field description value coding
ddr3 registered dimm imsh[4g/8g]pxxa1f2c advance internet data sheet rev. 0.50, 2008-01 26 01292008-3x8m-8frf contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 speed bins and timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 speed bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 package outline diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
edition 2008-01 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein an d/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any ki nd, including without limitation warranties of non-infringement of in tellectual property righ ts of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com advance internet data sheet

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